Increasingly, integrated circuits (IC) are becoming more powerful, with more functionality included in an IC chip. For example, a system on chip (SOC) may integrate numerous components of a computing system into a single integrated circuit chip and may include digital, analog, mixed-signal, and radio-frequency functions in a single chip. With an increase in the number of functions included in a chip, the demand for greater number of input/output (I/O) pins is also increasing. However, it may not always be feasible to provide a large number of I/O pins because of limitations in the size, complexity and/or cost of the chip.
A multiple function I/O pin may be used in a chip, which allows some flexibility in the usage of an I/O pin. As the name suggests, a multiple function I/O pin may be used for various purposes, based on a usage model of the chip, and may result in a reduction in pin count of the chip. FIG. 1 illustrates an exemplary block diagram of a multiple function pin interface (MFPI) 10. The MFPI 10 may include a plurality of function-out buses 34 (F1, . . . , F8) and a plurality of function-in buses 38 (M1, . . . , M4). Note that the number of function-out bus 34 and function-in bus 38 are purely exemplary in nature. In various embodiments, it may be intended to couple only one of the function-out buses 34 and/or only one of the function-in buses 38, at any given time, to an I/O pin 14 included in the MFPI 10. The I/O pin 14 may be coupled to a multiplexer 22 and a demultiplexer 26 through an I/O pad 18, which may control one or more functions of the I/O pin 14. One or more programmable registers 30 may control the operation of the multiplexer 22 and the demultiplexer 26. The programmable registers 30 may be programmed to couple a selected one of the function-out bus 34 and/or a selected one of the function-in bus 38 to the I/O pin 14 at any given time, based on a usage model of the chip in which the MFPI 10 is included. Thus, if it is intended to output function-output signal F3 to the I/O pin 14, it may be achieved by programming the programmable registers 30 and the multiplexer 22 accordingly.
As will be readily understood by those skilled in the art, several well known components of the MFPI 10 (e.g., input enable, output enable, drive strength control, slew rate control, pull up, pull down, etc.) have not been illustrated in FIG. 1 for the purpose of clarity.
FIG. 2 illustrates an exemplary block diagram of a multiplexing system 50, which may be used in the MFPI 10 of FIG. 1. In various embodiments, the multiplexing system 50 may be used as the multiplexer 22 of FIG. 1, and may include a plurality of multiplexers 54, 58, 62 and 66. In various embodiments, one or more programmable registers (not illustrated in FIG. 2), as stated previously with reference to the programmable register 30 of FIG. 1, may be used to control one or more of the multiplexers 54, 58, 62 and 66 of FIG. 2. The multiplexing system 50 may implement a differential timing priority for the function-out bus signals F1, . . . , F7. For example, the signal F1 may be coupled to the output Fout through only one multiplexer (multiplexer 66), while other signals (e.g., F3) may be coupled to the output Fout through a higher number of multiplexers (e.g., multiplexers 58, 62 and 66). Thus, the signal F1, if selected, may reach the output Fout in less time, whereas other function-out signals, if selected, may take more time to reach the output Fout, based at least in part on the number of multiplexers the signals have to traverse through before reaching the output. In various embodiments, the delay block 70 may be utilized to overcome certain design issues, e.g., hold time, etc. As will be apparent to those skilled in the art, in various embodiments, signal F1 may be the highest priority function-out bus signal, F2 may be the next highest priority function-out bus signal, and so on, and F7 may be the lowest priority function-out bus signal.
It should be apparent that the multiplexing system 50 is exemplary in nature, and a different number and/or configuration of the individual multiplexers may also be possible. Additionally, a differential timing priority demultiplexing system may also be envisioned by those skilled in the art for the demultiplexer 26 of FIG. 1.
The MFPI 10 of FIG. 1, optionally along with the multiplexing system 50 of FIG. 2, may be used to reduce the pin count of a chip. For example, using the MFPI system, only one I/O pin may be used for the plurality of function-out signals F1, . . . , F7 and the plurality of function-in signals M1, . . . , M4. Without the MFPI 10, each function-out signal and each function-in signal would have required a separate I/O pin.
In spite of its various advantages, however, the MFPI 10 may also have a few drawbacks. For example, the chip in which the MFPI 10 may be included may be a generic chip, the use of which may depend on a usage model of the chip. That is, a usage model of the chip may define which of the function-out bus and the function-in bus may be connected to the I/O pin 14. For example, for a first usage model required by a first user of the chip, the chip may always couple the F3 and M2 signals to the I/O pin 14; while for a second usage model required by a second user, the chip may always couple the F4 and M3 signals to the I/O pin 14.
Although the multiplexer 22 and the de-multiplexer 26 may have the required flexibility to enable the chip to be used for either the first usage model or the second usage models, the timing issues discussed previously with respect to the multiplexing system 50 may pose certain difficulties. For example, according to the first usage model, the F3 signal may be coupled to the I/O pin 14. However, the F3 signal may have to undergo a certain delay (as the signal needs to pass through three multiplexers before reaching the output pin) when trying to reach I/O pin 14. Also, during the last phase of the design stage (or immediately before tape-out and/or manufacturing) of the chip, it may not be easily possible to change the configuration of the multiplexer 22 of FIG. 1 or the multiplexing system 50 of FIG. 2, on the fly, to make F3 the highest priority signal, because such a change in the configuration may affect several other timing issues related to various other signals and components of the chip. Thus, a chip designed for the previously discussed first usage model may not be easily re-designed for the second usage model. Also, there may be situations where even larger numbers of function-in and function-out signals may be intended to be coupled to the I/O pin 14, which may necessitate a more complex multiplexing system 50.